Personally I don’t think we are going to see the line between memory and storage be all that muddled in the future. Yes, 3D XPoint is much more responsive than Flash. However Flash isn’t all that spectacular as is. The typical laborious drive has access latencies around 4ms on common. Flash can reach nicely bellow µs latency, however for very small arrays. That is expensive and principally seen in Microcontrollers that execute instantly from their Flash. "Enterprise grade" flash that optimizes at value/GB may have far increased latency, in the few to tens of µs region. 3D Xpoint is a bit of a wash. I have seen quoted figures of sub 350ns write latency, but that is likely for a single cell, not an array. Optane modules from Intel however have typical latencies around 5-15µs, but that is from a "system" perspective, ie, protocol and controller overhead comes into play, in addition to one’s software program surroundings.

DRAM then again has access latencies around 2-15ns at present. The issue with latency is that it results in our processor stalling resulting from not getting the data in time. One can prefetch, however branches makes prefetching harder, since what aspect do you have to fetch? Branch prediction partly solves this subject. But from a efficiency standpoint, we should always fetch each sides. But when we now have more latency, we need to prefetch even earlier, risking more branches. In other words, peak bandwidth required by our processor increases at an exponential rate in comparison with latency. A fee that is software dependent as nicely. Caching might seem like the trivial answer to the problem, but the efficiency of cache is proportional to the latency. To a level, cache is a magic bullet that simply makes memory latency disappear. But every time an application calls for one thing that isn’t in cache, then the application stalls, as long as there is threads to take its place that even have data to work on, then you won’t have a performance deficit aside from thread switching penelties, but when you don’t have such threads, then the CPU stalls.
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One can ensure that more threads have their information by just making the cache greater, however cache is rather a lot dearer than DRAM. Ultimately, it all results in the fact that rising latency will require an arbitrary quantity extra cache for an identical system performance. Going from the few ns latency of DRAM to the couple of µs latency of current persistent memory shouldn't be practical as an precise alternative for DRAM, even when it reduces its latency to a one centesimal it continues to be not impressive so far as memory goes. Although, using persistent DIMMs for storage caching or as a "RAM drive" of kinds nonetheless has major Memory Wave Routine benefits, but for program execution it is laughable. And that i don’t suspect this to vary any time soon. However I can see a future where the main memory relocates into the CPU. Where the CPU itself has an HBM memory chip or 4 on it supplying relatively low latency and high bandwidth Memory Wave Routine to the CPU, whereas the exterior buses are used for IO and storage. However this isn’t all that lifelike in additional professional purposes, Memory Wave since some workstation purposes honestly wants 10’s-100’s of GB of precise RAM to get good performance.

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